Mapping graphs onto core-based neuromorphic architectures
US9852370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a method for mapping a bipartite graph onto a neuromorphic architecture comprising of a plurality of interconnected neuromorphic core circuits. The graph includes a set of source nodes and a set of target nodes. The method comprises, for each source node, creating a corresponding splitter construct configured to duplicate input. Each splitter construct comprises a first portion of a core circuit. The method further comprises, for each target node, creating a corresponding merger construct configured to combine input. Each merger construct comprises a second portion of a core circuit. Source nodes and target nodes are connected based on a permutation of an interconnect network interconnecting the core circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.