Write enhancement for one time programmable (OTP) semiconductors
US9852805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.