Wafer back-side polishing system and method for integrated circuit device manufacturing processes
US9852899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jan 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.