Vertical power transistor with dual buffer regions
US9852910B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | May 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.