Method of manufacturing semiconductor device for reducing grain size of polysilicon
US9852912B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.