Patent · US Active

Systems and methods for high-speed, low-profile memory packages and pinout designs

US9853016B2 · kind B2 · utility

0Cited by
5References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 17, 2017
Grant dateDec 26, 2017
Priority date
Expiry dateFeb 17, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3025
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.