Semiconductor device and method for manufacturing same
US9853052B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.