Method of fabricating a lateral insulated gate bipolar transistor
US9853121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2015 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jul 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.