Floating grid and crown-shaping poly for improving ILD CMP dishing
US9853149B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Oct 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.