Phase domain calculator clock, ALU, memory, register file, sequencer, latches
US9853649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Sep 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.