Dual boot panel SWAP mechanism
US9858083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2014 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.