Emulated legacy bus operation over a bit-serial bus
US9858235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2012 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Sep 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.