Timing circuit for memories
US9858988B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.