Memory device
US9859005B2 · kind B2 · utility
17Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2015 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Mar 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array. The method includes computing marker bit values for each row of data in the memory array, and performing a Boolean OR operation on the marker bit values to generate a responder signal value. Also disclosed is a memory device including a memory array of memory cells arranged in rows and columns, and responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.