Method for forming improved liner layer and semiconductor device including the same
US9859157B1 · kind B1 · utility
8Cited by
44References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N2) and ammonia (NH3) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.