Patent · US Active

Integrated circuits having reduced dimensions between components

US9859210B2 · kind B2 · utility

0Cited by

2References

16Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Stanley Seungchul Song · San Diego, US
Choh Fei Yeap · San Diego, US
Da Yang · San Diego, US

Key dates

Filing date	Jun 19, 2015
Grant date	Jan 2, 2018
Priority date	—
Expiry date	Jun 19, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0186
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.