Semiconductor structure and a manufacturing method thereof
US9859254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Aug 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.