Integrated circuit device and method of fabricating the same
US9859393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2017 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jan 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.