Node isolation for protection from electrostatic discharge (ESD) damage
US9859704B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2017 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jan 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.