Delay cell and delay line having the same
US9859880B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00032
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.