Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot
US9859903B2 · kind B2 · utility
8Cited by
1References
21Claims
0Family size
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Key dates
| Filing date | Jan 29, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.