Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache
US9864695B2 · kind B2 · utility
2Cited by
19References
11Claims
0Family size
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Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.