Method and apparatus for decoding commands
US9865324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Oct 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.