Temperature compensated read assist circuit for a static random access memory (SRAM)
US9865333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Apr 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.