Method to produce a semiconductor wafer for versatile products
US9865503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.