Method for FinFET integrated with capacitor
US9865592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.