Electronic device
US9865799B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a pinned layer having a pinned magnetization direction; a free layer having a changeable magnetization direction; a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide; and a carbon-based compound patch positioned at one or more of between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, and in the tunnel barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.