Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode
US9865813B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or “confinement zone,” for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.