Selective segment via plating process and structure
US9867290B2 · kind B2 · utility
6Cited by
18References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10303
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.