Semiconductor memory device for performing a post package repair operation and operating method thereof
US9870837B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fall data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.