Resistance mitigation in physical design
US9871039B2 · kind B2 · utility
3Cited by
0References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.