Three-dimensional memory device having ring-shaped etch-stop patterns interposed between lower and upper layer stacks
US9871052B2 · kind B2 · utility
18Cited by
3References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Mar 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first stack including a plurality of alternating layers of first interlayer insulating layers and first conductive patterns; a second stack including a plurality of alternating layers of second conductive patterns and second interlayer insulating layers, the second stack being positioned above the first stack; a plurality of pillar-structures each pillar structure passing through the first and second stacks; and a ring pattern layer disposed between the first and second stacks, the ring pattern layer comprising a plurality of ring patterns, each ring pattern surrounding each pillar-structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.