Stacked capacitor with enhanced capacitance and method of manufacturing the same
US9871095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.