Checkpointed buffer for re-entry from runahead
US9875105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2012 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.