Method for planarizing material layer
US9875909B1 · kind B1 · utility
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1References
18Claims
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Key dates
| Filing date | Jul 26, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Jul 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.