Chip package and manufacturing method thereof
US9875912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.