Semiconductor package having stacked chips and a heat dissipation part and method of fabricating the same
US9875992B2 · kind B2 · utility
4Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2015 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Aug 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.