Thin-film transistor array substrate and manufacturing method thereof
US9876037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2015 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a thin-film transistor array substrate and a manufacturing method thereof. In the thin-film transistor array substrate of the present invention, the portion of the gate insulation layer interposed between two electrode plates of the storage capacitor is smaller than that of the remaining portion of the gate insulation layer so that the thickness of the insulation layer of the storage capacitor is reduced and the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved. The manufacturing method of a thin-film transistor array substrate of the present invention provides uses a half tone masking operation and applies two etching operations to have a portion of a gate insulation layer that is located on a first electrode plate of a storage capacitor partially etched so as to reduce the thickness thereof, thereby reducing the thickness of the internal insulation layer of the storage capacitor, whereby the area of the opposite surfaces of the capacitor electrode plates can be reduced under the condition of achieving the same capacitance and thus the aperture ratio is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.