Transistor with hole barrier layer

US9876082B2 · kind B2 · utility

Assignee

• MACOM Technology Solutions Holdings, Inc. · US

Inventors

• Allen W. Hanson · Cary, US
• Gabriel R. Cueva · Bedford, US
• Wayne Mack Struble · Franklin, US
• Yan Zhang · Lanzhou, CN

Key dates

• Filing date: Apr 30, 2015
• Grant date: Jan 23, 2018
• Expiry date: Jan 20, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/602

Abstract

An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.