Patent · US Active

Processor support for hardware transactional memory

US9880848B2 · kind B2 · utility

1Cited by

20References

18Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Jaewoong Chung · Suwon-si, KR
David S. Christie · Austin, US
Michael P. Hohmuth · Dresden, DE
Stephan Diestelhorst · Dresden, DE
Martin T. Pohlack · Dresden, DE
Luke Yen · Ayer, US

Key dates

Filing date	Jun 11, 2010
Grant date	Jan 30, 2018
Priority date	—
Expiry date	Dec 14, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/467
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.