Sense amplifier and method for bit line voltage compensation thereof
US9881677B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2017 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Apr 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.