In line critical path delay measurement for accurate timing indication for a first fail mechanism
US9882564B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2017 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Mar 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.