Patent · US Active

Resource mapping in multi-threaded central processor units

US9886327B2 · kind B2 · utility

0Cited by

9References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Khary J. Alexander · Poughkeepsie, US
Markus Helms · Eppelheim, DE
Christian Jacobi · West Park, US
Bernd Nerz · Eppelheim, DE
Volker Urban · Gummersbach, DE

Key dates

Filing date	Nov 30, 2015
Grant date	Feb 6, 2018
Priority date	—
Expiry date	Nov 30, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F8/45
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.