Verification of circuit structures including sub-structure variants
US9886753B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.