Memory with controlled bit line charging
US9887011B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2017 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array and bit lines coupled to the memory array. A voltage source is included for supplying a voltage used during a charging operation. Bit line clamp transistors, such as bit line clamp transistors, are coupled to the voltage source, and configured to regulate current on the corresponding bit lines in response to a bit line control signal. A control circuit generates the bit line control signal in response to a feedback signal. A feedback circuit is provided that is coupled to the voltage source and produces the feedback signal. The feedback circuit senses load of the bit lines being charged. The load of the bit lines being charged can be sensed by sensing the magnitude of the current from the voltage source during the charging operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.