Fan-out semiconductor package structure and fabricating method
US9887148B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2017 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Feb 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.