Multiple pre-clean processes for interconnect fabrication
US9887160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive material, the opening extending from a first surface to a second surface of the dielectric material layer and being in contact with a portion of the substrate; performing a plasma treatment process to chemically enrich exposed surfaces of the dielectric material that line the opening to form a chemically-enriched dielectric surface layer that included an element in a higher concentration than a remaining portion of the dielectric material layer; performing a chemical treatment process to remove a metal contact product from the portion of the substrate that is in contact with the opening; and disposing a conductive material in the opening to substantially fill the opening and form the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.