Patent · US Active

Multi-layer metal pads

US9887170B2 · kind B2 · utility

0Cited by
2References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 11, 2017
Grant dateFeb 6, 2018
Priority date
Expiry dateMay 11, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/35121
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.