Memory calibration abort
US9891853B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2016 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Mar 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.