256-bit parallel parser and checksum circuit with 1-hot state information bus
US9891985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parser and checksum circuit includes a 256-bit data bus, IPV4, IPV6, TCP, and UDP state signal buses, a checksum summer and compare circuit, four 64-bit parsing circuits, a V6 extension processor, and a parse state context circuit. Each of the 64-bit parsing circuits includes two 32-bit parsing circuits. The data bus receives a data signal that is part of a packet. IPV4, IPV6, TCP, and UDP state signals are each configurable into 1-hot states where at most 1-bit is digital logic high. Each of the 1-hot states corresponds to a segment of a packet header of one of the IPV4, IPV6, TCP, and UDP protocols. Each 32-bit parsing circuit receives a 1-bit shifted version of the state signals received by the adjacent 32-bit parsing circuit and receives a portion of the data signal. State signals and the data signal portion are received in parallel during a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.